(1). Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to define a contact or via opening in a group of dielectric layers to expose an underlying conductive or isolation region of a semiconductor device.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed improved device performance to be realized while still reducing the fabrication cost for the same semiconductor chips, comprised with the higher performing devices. Smaller features allow performance degrading parasitic capacitances to be reduced, while a greater number of smaller, higher performing semiconductor chips obtained from a specific size starting semiconductor substrate, result in a reduced fabrication cost for each specific semiconductor chip. The reduced area allotted to each semiconductor chip can however present difficulties not encountered for less dense semiconductor chips. For example contact or via openings formed in a group of dielectric layers, used to expose an underlying conductive region and to subsequently accommodate a conductive via structure, can no longer afford the benefit of being fully landed on the underlying conductive region. The ability to form a non-fully landed contact or via opening, referred to as a borderless opening, is dependent on the ability of the etching procedure to completely remove dielectric material from all openings independent of the thickness uniformity of the dielectric layer across the entire semiconductor substrate. An over etch cycle used for the contact opening procedure, employed to insure complete removal of dielectric material independent of thickness uniformity, has to feature excellent selectivity to the exposed underlying materials so that the etch procedure terminates or significantly slows at end point. Unwanted removal of exposed conductive or insulator material during the over etch cycle can result in reduced device performance or yield loss.
This invention will describe a procedure for defining a contact or via opening in a stack of dielectric layers featuring a novel tri-layer composite located as the underlying material of the stack of dielectric layers. The etch rate selectivities of the components of the tri-layer composite allow a dielectric over etch cycle to be employed without risk of penetrating or removing the conductive or insulator regions needed to be exposed in the contact or via openings. Prior art such as Visokay et al, in U.S. Pat. No. 5,972,722, Hong, in U.S. Pat. No. 5,596,230, Parat et al, in U.S. Pat No. 5,731,242, and Wu et al, in U.S. Pat. No. 6,080,674, describe methods of forming self-aligned contact and via openings using underlying etch stop layers. None of these prior art however describe the unique tri-layer composite employed in the present invention, allowing the contact opening procedure to employ an over etch cycle without the risk of attacking or removing exposed underlying regions of the semiconductor device.